Complex integrated circuits (ICs) can be designed using various levels of abstraction. Using a hardware description language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and higher logical levels. When designing using an HDL, the designer describes the behavior of a system in terms of signals that are generated and propagated from one set of registers to another set of registers through combinatorial logic modules. HDLs provide a rich set of constructs to describe the functionality of each module. Modules may be combined and augmented to form even higher-level modules.
System-level integration may rely on reuse of previously created designs that have been provided either from within an enterprise or from a commercial provider. Libraries of pre-developed blocks of logic have been developed that can be selected and included in a circuit design. Such logic blocks include, for example, adders, multipliers, filters, and other arithmetic and digital signal processing (DSP) functions from which system designs can be readily constructed. The logic blocks may further include memories and storage elements. The engineering community sometimes refers to these previously created logic blocks as “design modules,” “cores,” “IP cores” (intellectual property cores), or “logic cores,” and such terms may be used interchangeably herein. The use of pre-developed IP cores permits faster design cycles by eliminating the redesign of circuits. Thus, using IP cores from a library may reduce design costs. Such IP cores may often be available for purchase by parties who desire the functionality provided by the IP core. IP cores include a circuit design in the form of source code or a netlist that may be used in implementing the design in a programmable IC, such as a field programmable gate array (FPGA). The core may be integrated into a design by instantiating the code or netlist. The logic core is then placed and routed along with the rest of the design to provide the desired functionality.
Incorporation of a logic core into a larger design, however, may not be a simple task. For example, different IP cores included in a signal processing design may be configured to operate on different dimensions of a data stream. For instance, in some communication systems, data may be received as codewords over a number of antennas, over a number of channel frequency bands, and/or over a number of time slots, etc. A first component of the signal processing design may be configured to output data as a set of codewords, whereas a next component of the signal processing design may be configured to receive data in the frequency domain as a set of subcarriers.
Due to the mismatch between the components, the components may not be able to be connected together directly without reformatting the data. To accommodate the mismatch in formats between the two components, sets of codewords may be buffered until complete sets of sub-carriers are obtained for input to the second component. Manual implementation of such buffers to perform such reformatting can be an error prone and time-consuming process. Further, such manual implementation requires designers to possess a requisite knowledge of data format requirements of each of the components in the signal processing design, which may be cumbersome to obtain.